Window-type semiconductor packages are advanced packaging technology, characterized by forming at least an opening penetrating through a substrate, allowing a chip to be mounted over the opening, and electrically connected to the substrate by bonding wires through the opening. One benefit achieved by this window-type package structure is to shorten length of the bonding wires, thereby making electrical transmission or performances between the chip and the substrate more efficiently implemented.
A window-type ball grid array (WBGA) semiconductor package 1 is illustrated in FIG. 4, wherein a substrate 10 has an upper surface 100 and a lower surface 101, and is formed with an opening 102 penetrating through the same. A chip 11 is mounted on the upper surface 100 of the substrate 10 in a face-down manner that, an active surface 110 of the chip 11 faces toward and covers the opening 102, allowing bond pads 111 formed on the active surface 110 to be exposed to the opening 102. A plurality of bonding wires 12 are formed through the opening 102 and bonded to the exposed bond pads 111 of the chip 11, so as to electrically connect the active surface 110 of the chip 11 to the lower surface 101 of the substrate 10. Then, a lower encapsulant 13 is formed on the lower surface 101 of the substrate 10 by a printing process, for encapsulates the bonding wires 12 and sealing the opening 102. And, an upper encapsulant 14 is formed on the upper surface 100 of the substrate 10 by a molding process for encapsulating the chip 11. Finally, a plurality of solder balls 15 are implanted on the lower surface 101 of the substrate 10 at area outside the lower encapsulant 13, and serve as input/output (I/O) ports of the semiconductor package 1 for electrically connecting the chip 11 to an external device such as printed circuit board (PCB, not shown).
However, due to material mismatch in coefficient of thermal expansion (CTE) between the upper encapsulant 14 (formed by a resin compound such as epoxy resin) and the chip 11 directly in contact with the upper encapsulant 14, under a high temperature condition such as curing of the upper encapsulant 14 or subsequent thermal cycles, the chip 11 particularly at corner or edge positions thereof would be subject to relatively greater thermal stress from the upper encapsulant 14. This may thereby cause cracks of the chip 11 at the corner and edge positions, and undesirably extend to damage other area of the chip 11; such a case may more seriously and easily occur for relatively longer or larger chips, and adversely degrade quality and the yield of fabricated package products.